DRC/LVS Development Engineer (職位編號(hào):tsmcnj000342)
面議
應(yīng)屆畢業(yè)生
學(xué)歷不限



- 全勤獎(jiǎng)
- 節(jié)日福利
- 不加班
- 周末雙休
職位描述
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崗位職責(zé):1.Work closely with process RD team to develop DRC/LVS for design readiness.2.Provide customer support to world-wide leading design house.3.Initial more innovation to continue optimize development efficiency.4.Work closely with various departments (Physical design/integration/Device RD/Product/ESD) on their design requirements.5.Work closely with EDA partner for tool qualification and methodology enhance.任職要求:1.Good knowledge of semiconductor FEOL/BEOL process and chip design concepts. Solid understanding of device physics, Layout design is a plus.2.Knowledge of EDA partner (Mentor, Synopsys, Cadence, etc.) tools suite is a plus. Especially Laker / Virtuoso / Calibre.3.Scripting and programming experience using several of the following: Perl, Python, C, C , TCL, Skill.4.Ability to work across teams to drive a solution, problem solver and self-motivated.5.The ideal candidate will have experience in DRC/LVS development.6.MS or above in EE, CS related fields.
職能類別:集成電路IC設(shè)計(jì)/應(yīng)用工程師
工作地點(diǎn)
地址:南京江寧區(qū)南京-江寧區(qū)


職位發(fā)布者
HR
臺(tái)積電(南京)有限公司

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電子技術(shù)·半導(dǎo)體·集成電路
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200-499人
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外商獨(dú)資·外企辦事處
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浦口經(jīng)濟(jì)開(kāi)發(fā)區(qū)紫峰路16號(hào)